An analog and digital circuit mixed technique is important for an LSI (Large-Scale Integrated circuit). In such a circuit, noise measurements would become important due to miniaturization and low power supply voltage of the LSI. Specifically, when an analog-to-digital (A/D) conversion circuit is mounted on a chip on which a digital circuit is mounted, noise becomes important which is synchronized with a clock signal sent from the digital circuit and propagated through a substrate. The A/D conversion circuit includes a sampling and holding circuit and a comparator. The sampling and holding circuit samples an analog signal and holds the sampled analog value. The comparator compares the sampled analog value with a reference analog value to output a comparison result as a digital value. Thus, the A/D conversion is carried out. Here, the sampling and holding circuit has a high noise sensitivity and receives influence on characteristics, especially, an A/D conversion characteristic. In such a situation, it is well known to shift a sampling and holding timing from a clock signal timing in the digital circuit for the noise measurement.
However, if the scale of the digital circuit becomes large so that a digital circuit operation becomes complicated, it is more difficult to set to an optimal value, a phase difference between the sampling and holding timing in the A/D conversion circuit and the clock signal timing in the digital circuit. Moreover, if influence of a manufacturing variation and a temperature drift is taken into consideration, it is impossible to set an optimum phase difference in advance.
Japanese Patent Publication (JP 2000-196451A) discloses a conventional A/D conversion circuit in which a noise sensitivity is suppressed by adjusting the sampling and holding timing. The conventional A/D conversion circuit is incorporated in an LSI semiconductor chip and includes an A/D converter and a clock phase adjusting circuit. The clock phase adjusting circuit includes delay elements (e.g. inverter circuits) and sets a plurality of phase differences in advance by combinations of the delay elements after completion of the semiconductor chip. In the conventional A/D conversion circuit, if the A/D converter only provides an insufficient A/D conversion precision because of power supply noise, a timing difference is changed between a generation timing of the power supply noise from a logic circuit section and a timing of a clock signal supplied to the A/D converter by the clock phase adjusting circuit in response to an instruction, even after completion of the LSI semiconductor chip. Thus, the conventional A/D conversion circuit carries out A/D conversion without influence of the power supply noise from the logic circuit section. The manufacturing variation and the temperature drift are not taken into consideration in this timing difference.
When the timing difference between a sampling and holding timing in the A/D conversion circuit and a timing of noise propagated through the substrate due to clock signal for a digital circuit is to be set in advance, it is impossible to adjust the sampling and holding timing to an optimum value because of the noise amplitude and noise phase which depend on the manufacturing variation and the temperature drift.
What is considered as a mechanism of noise generation in general is charging/discharging in a power supply terminal and a ground terminal in transition of a CMOS logic gate. In this case, noise which contains a frequency component due to an inductance component existing parasitically in a digital circuit and a change of a current is generated and the noise is partially propagated into a substrate. In this case, the current is variable depending on changes of an operational voltage and an operation temperature and manufacturing variation, so that the noise amplitude changes. Accordingly, even if a phase difference is set after completion of a semiconductor chip in a conventional A/D conversion circuit, the set phase difference is not optimum to the phase and amplitude of noise in a usage state by a user.